A typical processing system with video/graphics display capability includes a central processing unit (CPU), a display controller coupled with the CPU by a CPU bus, a system memory also coupled to the CPU bus, a frame buffer coupled to the display controller by a local bus, peripheral circuitry (e.g., clock drivers and signal converters), display driver circuitry, and a display unit. Additionally, the system may include peripheral controllers, such as those necessary to control a CD ROM drive, hard-disk drive, floppy disk drive, printer, to name a few options.
The CPU generally provides overall system control and, in response to user commands and program instructions retrieved from the system memory, controls the contents of graphics images to be displayed on the display unit. The display controller, which may for example be a video graphics architecture (VGA) controller, generally interfaces the CPU and the display driver circuitry, controls exchanges of graphics and/or video data with the frame buffer during display update and refresh operations, controls frame buffer memory operations, and performs additional processing on the subject graphics or video data, such as color expansion.
The frame buffer stores words of graphics or video data defining the color/gray-shade of each pixel of an entire display frame during processing operations such as filtering or drawing images. During display refresh, this "pixel data" is retrieved out of the frame buffer by the display controller pixel by pixel as the corresponding display pixels on the display screen are generated. The display driver circuitry converts digital data received from the display controller into the analog levels required by the display unit to generate graphics/video display images. The display unit may be any type of device which presents images to the user conveying the information represented by the graphics/video data being processed. The "display" may also be a printer or other document view/print appliance.
In order for the CPU to communicate with a given subsystem or resource, for example the display controller, the system memory or one of the peripheral controllers, the CPU must be capable of individually addressing that subsystem. In currently available systems, the CPU primarily communicates with the subsystems through "glue" or "core" logic. The glue (core) logic is typically programmed to assign each subsystem a unique set of addresses in the CPU address space as a function of socket or board position. The core logic then routes requests for access and/or commands to a selected subsystem via the expected socket. This technique is inflexible since subsystem function and the corresponding physical socket are inseparable. Thus for example, if a socket is assigned to maintain a memory module of a certain address space, it becomes impossible to insert therein a pin compatible module whose function is that of a graphics controller.
One specific instance where communication between the CPU and the various subsystems is important is during display generation and update. This is particularly true in high speed/high resolution display systems, where it may be desirable to distribute the display data processing tasks. In this case, the CPU must be able to efficiently access each of the various processing resources as required to effect display updates and other display control functions. Once this is done, the subsystems can manage simple tasks such as display refresh while the CPU is available to attend to more critical tasks.
Thus, the need has arisen for circuits, systems and methods for communicating with the various processing, control and memory resources in an information processing system. In particular, such circuits and systems and methods should be applicable to the control of the resources necessary to implement high definition/high speed display systems.